The tools look amazing as well. You'll won't design the next Intel CPU on that 130nm process but to think that the Z80 will fit on 0.064 mm2 is just amazing.
It's great that there will still be an alternative to the official chip now that it won't be manufactured any more.
Now I want that gorgeous mauve ceramic package with a gold-plated cover over the chip...
https://twitter.com/l_vanek/status/1783557817133039738/photo...
Pentium III: 250 nm to 130 nm [0]
Pentium VI: 180 nm to 65 nm [1]
“The Katmai contains 9.5 million transistors, not including the 512 Kbytes L2 cache (which adds 25 million transistors), and has dimensions of 12.3 mm by 10.4 mm (128 mm²). It is fabricated in Intel's P856.5 process, a 250 nm complementary metal–oxide–semiconductor (CMOS) process with five levels of aluminum interconnect”
That’s 2,000 times the area of this 0.064 mm² Z80.
https://en.wikipedia.org/wiki/Pentium_III#Tualatin:
“The third revision, Tualatin (80530), was a trial for Intel's new 130 nm process”
I can’t easily find the die size if that.
A Z80 has a 4-bit ALU (https://en.wikipedia.org/wiki/Zilog_Z80#Microarchitecture), making even integer addition take quite a few cycles (15 for 16-bit addition, reading http://www.z80.info/z80time.txt)
And then there’s the clock speed difference. The first Pentium III ran at 450MHz, the fastest Z80 at 50MHz (https://en.wikipedia.org/wiki/Zilog_eZ80)
I think those two combined already will cost you a factor of around 100 in speed versus that pipelined Z80, much more versus a Z80 proper.
Things get worse if you want to add or subtract 32- or 64-bit integers (another factor of 2 or 4, ballpark)
If you want to do integer multiplication and division of any size and all floating point operations you will have to do those in software, and likely lose whatever speed advantage you might still have.
O, and each core will be limited to 64kB of memory. Those interconnects better be fast and use DMA, so you can keep computing while you shuffle data around.
> 160 x 100 um tile + ASIC + demonstration board: The standard price is $300 plus shipping.
> However, Efabless is sponsoring a special early bird offer of $150 (plus shipping), limited to one order per person.
> Each extra tile is $50, and extra analog pins start from $40 per pin.
Unless I am badly mistaken 160 x 100 um is .16 x .1 mm which means the tile is 0.016 mm2 meaning a 0.064 mm2 die takes four slots?
https://hackaday.com/2024/04/19/end-of-life-for-z80-cpu-and-...
https://en.wikipedia.org/wiki/Zilog_eZ80#Use_in_commercial_p...
https://arstechnica.com/gadgets/2024/04/after-48-years-zilog...
https://en.wikipedia.org/wiki/Zilog_eZ80
There must be millions floating out there. But with distributors like Mouser or Farnell gone, for anyone looking to buy some, it's eBay & co which tends to be a crapshoot.
Not the past decade, but two decades ago (2005) the z80 was still popular. At work, I was working on a product based on, IIRC, a Rabbit Semiconductor product, which was a module with on-chip ethernet. It was a Z80 running at 40Mhz.
Personally, I also had a little siemens organiser thing, that also was z80 based (not sure of the actual specs). I recall trying to write programs for it and failing (may not have been open; no way to reprogram or download new code to it, maybe).
[EDIT: The organiser was a siemens IC35]
https://floooh.github.io/virtualkc/p010_kc85.html
An "Adrian's Digital Basement" episode about the KC85/3:
Punch-Out!!
But most noteworthy is Galaga: Ran on 3, count 'em, 3, Z80's.
I still have my copy of Programming the Z80 that I got as a kid: https://en.wikipedia.org/wiki/Programming_the_Z80
In uni we built an 8088 board in microprocessor class and it was the best class I ever took; it demystified drivers and hardware for me. I attempted a redesign using KiCAD which added an IO expansion port and better layout with an LCD port for a 2x16 character LCD. I had a prototype made by Futurlec but made a massive mistake in footprint assignment that required an interposer. Furthest I got was soldering in the 8284 and the IC sockets then got distracted by life and its sitting in a box still.
Microcontrollers are great, everything in one package but there's something enormously satisfying about being able to design and build a computer by hand. FPGAs sort of bring this back but the tooling is byzantine dog shit.
For instance here's the LD A,(DE) "instruction payload":
https://github.com/rejunity/z80-open-silicon/blob/974c7711b2...
And here's the same machine cycle in my software emulator:
https://github.com/floooh/chips/blob/bd1ecff58337574bb46eba5...
Both set the address bus to the content of the DE register (and at the same time the MREQ|RD pins need to be set somewhere to indicate a memory read to the outside world, in my emulator this happens in the _mread macro), and in the next clock cycle load the data bus into the A register.
What's interesting though is that the Verilog implementation doesn't seem to update the internal WZ register with DE+1, which makes me wonder if undocumented behaviour is correctly implemented, but maybe updating WZ is handled elsewhere (there are references to the WZ register in other places).
In the end, if it looks and feels like a Z80 from the outside (e.g. the right pins are active at the right time) the internal implementation doesn't matter.
https://github.com/rejunity/z80-open-silicon/blob/974c7711b2...
Instruction decoding on a real Z80 CPU doesn't work at all like that :)
A non-emulator-approach would probably use the reverse engineered Z80 netlist from visual6502.org to base the design on, no idea if this is even doable with modern chip design tooling(?)
If anything, the netlist is useful to verify the Verilog implementation (as is mentioned here in the readme: https://github.com/rejunity/z80-open-silicon?tab=readme-ov-f...)
Verilog isn't imperative code, to be executed one line after another in sequence. It's a description of combinatorial logic to be wired up to inputs and outputs, gated by a clock edge. Everything in the Verilog module "runs" at the same time, there's no jumping to a branch, there is instead logic to wire up one "casez" block or another to the relevant output signals. All the blocks are lit up, only one has its output selected to connect to the output wires.
The PLA block is more convenient to a hardware engineer laying out a CPU by hand. You can see everything together and trace execution easily. Downstream consequences of decode are done elsewhere. Upstream decode of control signals are done elsewhere. The Verilog is more convenient to a hardware engineer relying on tools to route logic: the Verilog does more than the PLA - it does the additional control signal inputs, and it does the downstream consequences like determining which register(s) are used on which register bus. It's laid out more like a software decode of the instruction bits because it's easier to think about groups of opcodes than individual ones.
In execution, though, they wind up doing very similar things.
(I was on early efabless.com team) open source EDA.
No, because an ALU instructions with a register as source is already running as fast as possible (at 4 clock cycles, which is the duration of an opcode fetch 'machine cycle'). Or from a different perspective: an 8-bit ALU wouldn't have made math instructions faster, but would have cost twice as many transistors.
The 4-bit ALU is just an internal implementation detail that isn't visible to the outside (except maybe through the existence of the half-carry flag which indicated a carry from the lower into the higher nibble).
And if you want a CPU replacement that plugs directly into old home computers, the CPU needs to have the original instruction timing, otherwise software that depends on 'cycle counting' won't work (probably less of an issue on the ZX Spectrum though because the Speccy didn't have a programmable video hardware like for instance the Amstrad CPC).
The eZ80 is a modernised and more efficient design, with (among other things) a wider ALU: https://en.wikipedia.org/wiki/Zilog_eZ80. Not an option for keeping old home computers alive though, for this you'd want an exact Z80 clone with the original timings and undocumented behaviour.
Managed to produce a program where with key presses, you could change delay in the loop in +/- 1 clockcycle increments. Mind you: fastest Z80 opcodes take 4 cycles.
How then? Well, there's also opcodes that take 5 cycles. Or 6. Or 7. And 8=2*4, 9=4+5, etc. Program just automated the insertion/removal of those in the inner loop. Of course I had to pick instructions that didn't mess with some Z80 registers.
Great fun (& educational) figuring out stuff like that. Fun times...
I pretty much knew all the clock cycle counts for the instructions as a teenager, and you would code assembler with them always in mind.
Ah clever! Didn't think of that. Probably the closest thing to "racing the beam" since the Atari 2600 :)
https://github.com/rejunity/z80-open-silicon/blob/main/docs/...
https://github.com/rejunity/z80-open-silicon/blob/68438f0019...
So you'd get an effective 12.5MHz Z80 clock and need a bit of external logic to demultiplex the full IO interface. Still not too shabby!
The goal (per the project README) appears to be to prototype with TT07 and then look into taping out standalone with ChipIgnite in QFN44 and DIP40 packages (which would be able to have the full traditional Z80 bus interface and run at the full clock rate).
"Guy Hutchison (see TV80 project) has synthesized an early version of the core in a 130nm TSMC process. He determined the design to contain about 20k gates and run at about 240 Mhz. While the speed is somewhat less than "target", optimizations of the logic should increase this somewhat."
Guy Hutchison's TV80 is also mentioned on this project's page.
The cache would need to know about all bank-switching performed by the system, and understand how the memory banks are mapped into the memory space.
Could have:
* Plain read-only memory (you cache this)
* Plain RAM not shared with other devices (you cache this)
* Memory-mapped IO (you don't cache this)
* RAM shared with other devices where the other device does not write there, such as video memory (write-through cache, full read cache)
* RAM shared with other devices where the other device can write there (don't cache this)
https://www.e-basteln.de/computing/65f02/65f02/:
“The idea is to use this as a “universal” accelerator for 6502 and 65C02-based host computers – just plug it into the CPU socket. The only thing the FPGA board needs to know about its host is the memory map: Where does the host have memory-mapped I/O? Up to 16 different memory maps can be stored in the FPGA, and selected via a mini DIP switch. Upon power-on, the 65F02 grabs the complete RAM and ROM content from the host and copies it into the on-chip RAM, except for the I/O area. Then the CPU gets going, using the internal memory at 100 MHz for all bus accesses except for any I/O addresses – for these, the internal CPU pauses, and an external bus cycle is started at whatever the external clock speed is.”
I've never received a counterfeit Z80 that outright didn't work, but one thing to be keep in mind is that despite often being branded as CMOS 20Mhz (aka Z84C0020), half the time the chips I've received were lower grade or even worse, NMOS.