That aside, people usually learn about RDIMM the hard way when they need to get ECC unbuffered RAM for something like HEDT/workstation or tower server Xeon/i3/Ryzen with ECC support but buy the cheaper RDIMM instead of the ECC UDIMM modules only to figure out they don’t work!
AMD's Threadripper line has been inconsistent; the 5000 series was all Threadripper PRO parts, then last year's 7000 series brought back the non-PRO Threadripper options. But even the entry-level Threadripper CPUs and TRX50 motherboards available today are less affordable than HEDT systems were eg. 15 years ago. The high core counts available in mainstream desktop sockets have shifted the boundary between that segment and HEDT, and as a result there aren't good options to step up to a platform with more IO capability without also stepping up to really high CPU core counts.
My POV, ECC should be standard for inflight on all desktops. The majority of desktop (business and education) is used for content creation versus pure content consumption. And ECC needs to ditch 1 bit and move to 2 bit or more masking.
What?
https://www.corsair.com/us/en/c/memory/ddr5-ram
Plenty of two-stick kits there. Were you just trying to make up an excuse to pick Kingston over Corsair?
The Difference Between a Standard DIMM and a Cudimm or Csodimm [Crucial/Micron] (16.11.2024)
https://news.ycombinator.com/item?id=41090956
But you not only loose some capacity. Some bandwidth is also lost. And perhaps even some CPU cycles, since likely in-band ECC hasn't been implemented purely in a hard IP-block.
So the burst transfers have the same size as when ECC is disabled.
Without the special cache, the number of memory accesses would double, for data and for the extra ECC bits, which would not be acceptable. With the ECC cache, in many cases the reading and writing of the extra ECC bits can be avoided.
There have been published a few benchmarks for inline ECC. The performance loss depends on the cache hit rates, so it varies a lot from program to program. In some cases the speed is lower by only a couple percent, but for some applications the performance loss can be as high as 20% or 30%.
The cpu cache won't be mismatched though, since the memory controller can mask this. The performance hit will be due to the memory controller having to do the extra reads for parity.
That will be a tiny mismatch, and I wonder if the performance implication of this won't more or less be equal to the performance difference we already have between buffered and unbuffered memory (more or less the same, simply, now that "extra work", moved from inside the dimm, to the memory controller)
This helps, but ideally the entire path from CPU to Dimms is wider and covers not just what is being read or written, but also the address it's being written to. After all writing the correct bits to the wrong address is a serious failure.