Classic thyristors are useful only for controlling 50/60 Hz AC consumers.

Many applications that were done in the past with normal thyristors, for lack of alternatives, like electric motor control, are done now with GTO (gate turn-off) thyristors or with IGBTs (insulated gate bipolar transistors) or with silicon carbide transistors.

Even the use of GTO thyristors is regressing. If any thyristors will still be used in the future, they will use silicon carbide, with which they can be much faster than the silicon thyristors.

Like anything to do with metastability this is a statistical thing - it can do this, but it's highly unlikely.

I worked on a chip in the mid 90s where we were very careful about our clock crossings, dropped in special high-gain anti-metastability flops, designed logic to reduce synchronised signal frequencies etc etc all the good stuff - we calculated that we'd see a failure (and mostly that would be a pixel burble on the screen) every year or so - at the time Win95 couldn't stay up a week so management decided to ship it

Human Body Model: https://en.wikipedia.org/wiki/Human-body_model

Latchup testing: https://www.ti.com/lit/wp/scaa124/scaa124.pdf?ts=17555138993...

The life of a shipping container can be complicated and include being struck by lightning, the sea breeze, and 50°C in the sun in a car park.

Intel is covering its ass because there's always a subcontractor from an oil drilling company who will set up equipment in the middle of a sandstorm and say he didn't know it was a bad idea.

But keep in mind that final assembly and packaging is typically happening in large, air-conditioned halls with vinyl floors, conveyor belts, plastic office chairs, disposable coveralls, etc. There's more static zaps in places like that than in a home with wooden floors, reasonable humidity, and casual clothing.

And then, as Ken notes, there's the question of scale. If you statistically kill one chip in 200, you might not even notice that in a home lab. But for a manufacturer, that's more faulty devices shipping to customers than they want.

This is in a climate with fairly cold winters (-40°C and below isn't unheard of), so layers of wool clothing and very low humidity. It's been less of a problem recently because modern motherboards come with ESD protection, but 10-15 years ago shared computers with most USB ports no longer working were the norm.

I always touch ground before working on electronics, and often get zapped. It's a fairly common practice here AFAIK.

But one vital thing to understand is that a lot of those "vendor recommendations" exist to cover for rare 1% to 0.1% edge case failures.

You can put together 20 PCs, with none of them dying from ESD, and conclude that ESD "isn't a real issue". But if you have a company that puts together tens of thousands of PCs per month? Then those ugly 0.1% edge case failures WILL pop up and they WILL cost you. And if you employ enough people, one of them might be a son of Zeus with a wild Wimshurst machine hairstyle - capable of emitting two high power ESDs, complete with an audible crackle and a visible spark, per minute. So ESD straps it is.

The same applies to things like humidity control or reflow profiles for electronics. Not an issue ~99% of the time. The remaining ~1% can fuck you over in mass manufacturing, so disrespect the vendor at your own peril.

Moisture, clothing, habits play a role so it's highly variable.

It was interior Alaska, where humidity is low enough that an orange turns into a passable golf ball in a week and a half, so that was definitely a factor.

TLDR static electricity is bad for electronics, and damage does not necessarily show up as failure but often manifests as flaky behavior.

Piling on, but yes, you very well may have: https://www.youtube.com/watch?v=tcRqj9FhgcE

When you fry a chip is it obvious because you experience a zap?

If so, then that would make all this "make sure you're grounded" ceremony less mysterious — because unless you feel a zap (even a tiny one) you probably haven't fried a chip, and it doesn't generally happen in environments where you don't feel zaps.

Obvious caveat: "feeling" a zap is not a precise measurement. But perhaps "zaps fry chips" is a lie which reveals a greater truth.

Modern IC ESD protection is very effective against a few moderate energy events distributed on different pins, and there's a few industry standards that help determine the required amount of caution for dealing with a particular IC (HBM or human-body model, and CDM or charged-device model, are common - targeted toward human assembly procedures and things like triboelectric or inductive charge buildup). In the right climate, a single high energy event is sometimes enough to degrade functionality or (rarely) completely destroy the device, so board assembly and semiconductor manufacturing facilities still require workers to use wrist straps, shoe grounders, mats, treated floors, climate control, etc. Some high voltage GaN work I did years ago required ionizing blowers (basically a spark gap with a fan) because GaN gates are easy to destroy with gate overstress, and there are risks involved with unintended high voltage contact with typical ESD protective solutions. In another embedded-focused lab, the only time I've ever seen someone put on a wrist strap was for handling customer hardware returns. It really depends what you're working with, and in what environment.

I've more frequently (once or twice a year) had devices which exhibit symptoms of something being wrong at the inputs or the outputs, but only on a specific pin or port. For outputs, some symptoms include the output slew rate is inadequate, or the output appears stuck sometimes, or the output has higher than expected voltage noise (though this is a non-exhaustive list). For inputs, the symptoms are more complex - sometimes there's a manifestation at the outputs for amplifiers or other linear circuits, but for feedback systems or digital systems they might behave as though an input is stuck, toggling slowly, etc. which is difficult to distinguish from other, more common errors. I've also directly been the cause of several ESD failures, but in these cases the test objective was to determine the failure thresholds for the system, so I'm not sure that counts.

I've had a customer hardware failure that was eventually traced back to electrical overstress damage on a single pin of an IC near the corner of a board, right where someone might put their thumb if they were holding the board in one hand. In the absence of a better explanation, I suggested this was an ESD failure due to handling error. I never heard about it again, which is weak evidence in favor of a one-off ESD event.