Looks like RISC-V 32-bit integer and multiply and atomic instr extension. Floating point supported when compiling via gcc or similar the example apps (not by the emulator itself but by the compiler emiting the required software functions to emulate the floating point operations instead).
I think it is very clever. Very compact instruction set, with the advantage of being supported by several compilers.
Wrapper over this other project which is the one implementing the instruction set itself: https://github.com/cnlohr/mini-rv32ima
Kudos to both projects.
EDIT: Found this link in my notes as well: https://news.ycombinator.com/item?id=24900376
This looks like it has a smaller code footprint at least. I'm not sure RISC-V is a very good target for this sort of thing. E.g. decoding the immediates in software is going to be very slow, whereas in hardware it's fast.
But on the other hand it is a stable target and can be configured to be a lot simpler than WASM.
I like the single C file, but Docker if you want all the examples approach, that's really convenient for embedded.
Test coverage looks good as well, be interesting to see the metrics.
This would be quite cool for adding scripting to medical devices, avoiding the need to revalidate the "core" each time you change a feature.
An interesting comparison would be against an embedded WASM bytecode interpreter like https://github.com/bytecodealliance/wasm-micro-runtime, which is still much larger at 56.3K on a Cortex M4F. Maybe WASM is just a more complicated instruction set than the smallest RISCV profile?
Have you considered adding support for memory-mapped IO simulation? That would make it useful for testing IoT/microcontroller drivers without the actual hardware.