Sequential Optimal Packing for PCB Placement
11 points
2 days ago
| 3 comments
| blog.autorouting.com
| HN
crote
1 hour ago
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The problem is that PCB design is hard. Writing a "cost function" for placement is basically impossible when later design steps are going to introduce hard constraints, and earlier design steps are actually extremely flexible.

For example, the general rule-of-thumb is to place one 100nF decoupling capacitor per power pin. But in practice there isn't always space for that. Do you suboptimally route your critical high-speed traces to place one? Do you add additional board layers for it? Do you switch to a smaller (and more expensive to manufacture) capacitor package size? Do you more it further away from the chip - making it significantly less effective? Do you make two power pins share a single capacitor? Do you switch to a different IC package or even a completely different chip with an easier pinout?

What is the impact of your choice on manufacturing requirements, manufacturing cost, part cost, part availability, testability, repairability, EMC/FCC/whatever certification?

Every option could literally be free, cost tens of millions, or anything in-between. Parts documentation is already woefully incomplete as it is, trying to automate routing it by requiring people to provide data describing basically the entire world just isn't realistic.

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rcxdude
30 minutes ago
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I do think autorouting is largely a UI problem for this reason. Specifying the constraints is very difficult, especially when it's also tied into assessing stuff like power distribution (where the rule of thumb of 100nF is almost certainly suboptimal, proximity probably matters less than you would think, and you can wind up with too much capacitance, but actually evaluating what matters is so much more complex that unless it's really critical it tends to be not much better than a blind guess that most of the time works well enough. I really would like to figure out a better set of rules for this, something a bit less heavyweight than a full simulation but still at least vaguely quantitive in terms of tradeoffs).

To me innovation in autorouting means being able to 'have a conversation' with it: being able to easily adjust things and see the results and map out the tradeoffs would be very useful, but it doesn't seem like this is an area that's being pushed too hard.

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edg5000
1 hour ago
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I think using the vision decoder baked into modern LLMs is the way to go. Have the LLM iterate; make sure it can assert placement qualities and understands the hard requirements. I think it can be done.
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bestouff
55 minutes ago
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I tried having Opus 4.6 route a PCB for me last month. The result was afwul. I'd be interested if there was a working solution to this.
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IsTom
2 hours ago
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I wonder how a MIP solver would fare in this?
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