The best presentation I've seen about CPU performance related to pipelining, branch prediction, and speculative execution was Chandler Carruth's "Going Nowhere Faster" presentation at CppCon 2017 [0]. I do recommend watching the whole presentation, but if you watch nothing else then just watch the 5 minutes or so from the linked timestamp.

[0]: https://youtu.be/2EWejmkKlxs?t=2511

CPUs haven't worked like that in anything but a microcontroller for half a century

If anyone is interested, at https://sonic-rv.ics.jku.at/ we built an educational platform for web-based simulation and visualization of RISC-V processor architectures.

Our pipeline visualization is reconstructed from real RTL traces (you can run your on programs which are simulated using GHDL).

Under examples you can find some different architectures based on the Harris&Harris book on computer architecture.

Maybe it's just me, but the visualizations do not help me at all.

Now do a dynamic scheduling out of order engine with renaming, 20 pipes, speculative execution and hundreds of instructions in flight. I guess you could make a multi-person game for this.