key features: Custom 16-instruction Harvard ISA, 8-bit fixed format, 4 general purpose registers

Hardwired control unit built entirely from AND/OR gate logic matrix

Dual-phase clocking to eliminate race conditions

Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer Early-exit conditional branching that saves upto 25% cycles when conditions aren't met

Full design specification document with version control

Since this was our first time doing such teamwork and a new thing we used RISC based system that fetches an 8-bit instruction from Instruction memory 4 bits of which translate to an instruction the last two bits are for source and destination registers. There are a total of 4 registers in the system with two memory units namely Data SRAM and I SRAM, the system follows a Harvard architecture.

There are design discrepancies too since it was our first time designing such a system and on top of that completely hardwired too.

To solve the problem of cold booting a bootloader is present too that copies the contents of a temporary ROM into instruction RAM and then hands over the reins to the CPU.

We also implemented conditional branching as well as early exit branching too that only checks for zero or carry flag and branches without wasting cycles, if the conditions are not met the Program counter increments.

Moreover we also created a complete documentation with version control describing each necessary part assuming prior knowledge.

Please take a look at it at https://github.com/c0rRupT9/STEPLA-1

For future development I want to implement a RISC CPU using FPGA's and connect it to an actual DRAM. We are also selling the full spec document and Logisim files for $5 to fund our passion https://tcfdiq.gumroad.com/l/zyyux Thankyou!